Technical Report: The State of Reversible Sequential Logic Synthesis

This report provides an overview of the current state of reversible sequential logic. We assume that the reader has a basic knowledge of reversible logic. An overview of necessary information is provided in [1]. Most research in reversible logic has concentrated on synthesis techniques for combinational logic. Sequential logic synthesis requires the incorporation of memory cells and feedback in a circuit, which seems to violate the definition of reversible logic. Previous researchers who have investigated this problem have approached it from two avenues; those who have proposed theoretical structures (i.e. gates) for building sequential building blocks such as latches and flip-flops, for example [2] and [3] and those who have proposed physical designs for memory cells (e.g. RAM), for example [4]. Our interest is directed mainly at logic synthesis at the gate level, and so we will concentrate on the former. This report gives an overview of the proposed structures, and suggests new work in how these might be incorporated into logic synthesis techniques aimed at producing sequential reversible logic circuits.